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17-Output LED Driver/GPO with
Intensity Control and Hot-Insertion Protection
COMMAND BYTE IS STORED ON RECEIPT OF
STOP CONDITION
D15
D14
D13
D12
D11
D10
D9
D8
ACKNOWLEDGE FROM MAX6964
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
P
Figure 7. Command Byte Received
R/W
ACKNOWLEDGE FROM MAX 6964
ACKNOWLEDGE FROM MAX6964
ACKNOWLEDGE FROM MAX 6964
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX 6964 's REGISTERS
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX 6964
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
A
P
1
R/W
BYTE
AUTOINCREMENT MEMORY ADDRESS
Figure 8. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX 6964
ACKNOWLEDGE FROM MAX 6964
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX 6964 's REGISTERS
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX 6964
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
A
P
N
R/W
BYTE
AUTOINCREMENT MEMORY ADDRESS
Figure 9. n Data Bytes Received
WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS)
SCL
1
2
3
4
5
6
7
8
9
SLAVE ADDRESS
COMMAND BYTE
SDA S A6 A5 A4 A3 A2 A1 A0
0
A
0
0
0
0
0
0
0
1
A MSB
DATA1
LSB
A MSB
DATA2
LSB A
P
START CONDITION
R/W ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
STOP
CONDITION
O7–O0
O15– O8
t DV
DATA1 VALID
DATA2 VALID
t DV
Figure 10. Write Timing Diagram
If multiple data bytes are transmitted before a STOP con-
dition is detected, these bytes are generally stored in
subsequent MAX6964 internal registers because the
command byte address autoincrements (Table 2). A
diagram of a write to the output ports registers (blink
phase 0 registers or blink phase 1 registers) is given in
Figure 10.
Message Format for Reading
The MAX6964 is read using the MAX6964’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write (Table 2). Thus, a read is initiated by first configur-
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